EURASIP Open Library

Conference proceedings 1996-2017


By Year

Co-Authors

All publications by Sentieys, O. in 1998 (clear)


Asynchronous Timing Model For High-Level Synthesis Of Dsp Applications

Authors (alphabetically): Chillet, D.; Dedou, Okito; Sentieys, O.;

EUSIPCO, Rhodes, Greece, 1998


Vlsi Implementation And Complexity Comparison Of Residue Generators Modulo 3

Authors (alphabetically): Pedron, Fabrice; Piestrak, Stanislaw J.; Sentieys, O.;

EUSIPCO, Rhodes, Greece, 1998